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Quad SPI-3 to SPI-4 Link Layer
Lattice Semiconductor
Bridge Core User’s Guide
BUS models have been provided in the directory “lib\modelsim” as zip archives (spi_324l_o4_1_001.zip,
orca4_work.zip, orspi4_work.zip and sysbus_work.zip). These ?les should be unarchived into the directory
“lib\modelsim. All these work directories have to be refreshed before simulation can be run. A simulation script ?le
is provided in the “eval\simulation\scripts” directory for RTL simulation. The script ?le run_vsim.bat (for PC) uses
the precompiled models provided with this package. It calls the “run_qspi3_nocore.plx” perl script in the same
“scripts” directory. The paths to “MODELTECH” in the script ?le should be set to the appropriate MTI Modelsim ver-
sion value for the local system. The simulation is run by executing “scripts\run_vsim.bat” from the “eval\modelsim”
directory. A successful simulation is achieved when the “TEST PASSED” message is displayed at the end of the
simulation.
For more information on how to use ModelSim, please refer to the ModelSim User’s Manual.
Core Implementation
Lattice’s Quad SPI-3 to SPI-4 Link Layer Bridge evaluation package includes a Quad SPI-3 to SPI-4 Link Layer
Bridge user application and scripts for synthesizing, mapping and routing the Quad SPI-3 to SPI-4 Link Layer
Bridge IP solution.
The Quad SPI-3 to SPI-4 Link Layer Bridge evaluation package includes the following components:
? Basic Quad SPI-3 to SPI-4 Link Layer Bridge IP core;
? Verilog module that instantiates the ORSPI4 component and the ORCA4 SYSBUS with User Slave component,
providing a Motorola Power PC interface to the IP core’s register interface, as well as registers in the ORSPI4
embedded core;
This evaluation package is illustrated in Figure 10. The following Verilog ?les are provided:
? qspi3_link_params.v for the Quad SPI-3 to SPI-4 Link Layer Bridge core and top level parameters (Note: this ?le
and all IP parameter ?les must not be modi?ed in any way. If this ?le is modi?ed, this IP core may not run at spec-
i?cation);
? spi_324l_o4_1_001.v for the Quad SPI-3 to SPI-4 Link Layer Bridge core;
? mycore.v for the ORSPI4 module;
? sysbus_fpsc.v for the SYSBUS module;
? rfclk_hpll_bo.v for PLL;
? rfclk_pll_bo.v for PLL;
? fpga_io.v for IO SPI3 buffers;
? orspi.v for “qspi3_link” top-level module that ties all the application components together.
Note that the Quad SPI-3 to SPI-4 Link Layer Bridge Core is delivered as a gate-level netlist
(spi_324l_o4_1_001.ngo). Users can compile the entire design shown in Figure 10 to realize a turnkey solution, or
instantiate the Quad SPI-3 to SPI-4 Link Layer Bridge Core as a block box together with any of the other blocks
shown and/or their own designs, to realize a unique system-level project solution. Users may use orspi.v as a tem-
plate for their own application.
Implementing a design in an ORSPI4 device requires the ispLEVER software and an ORSPI4 FPSC Design Kit.
For more information, please contact your local Lattice Semiconductor sales representative or visit the Lattice web-
site at www.latticesemi.com.
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